A high resolution DDFS design on VHDL using Bipartite table method

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dc.contributor.authorAcar, Yunus Emre
dc.contributor.authorYaldız, Ercan
dc.date.accessioned2020-03-26T19:43:40Z
dc.date.available2020-03-26T19:43:40Z
dc.date.issued2017
dc.departmentSelçuk Üniversitesien_US
dc.description.abstractIn this study, a Look Up Table (LUT) based Direct Digital Frequency Synthesizer (DDFS) is designed on VHDL. Bipartite Table Method, an advance memory compression method, is used together with quadratic compression method. 23 mHz frequency resolution is achieved with 100MHz clock input. The required memory is obtained 585 times smaller than traditional DDFSs. A MATLAB code is revealed to select the best design which provides the smallest required memory for 100 dB Spurious Free Dynamic Range (SFDR) level. The contents of the LUTs are also evaluated by using MATLAB software. The design is simulated for multiple frequencies between 23mHz-30MHz with VIVADO 2016.3 software. The simulation results perfectly match with calculations.en_US
dc.identifier.doi10.21533/pen.v5i3.116en_US
dc.identifier.endpage313en_US
dc.identifier.issn2303-4521en_US
dc.identifier.issue3en_US
dc.identifier.scopusqualityQ2en_US
dc.identifier.startpage305en_US
dc.identifier.urihttps://dx.doi.org/10.21533/pen.v5i3.116
dc.identifier.urihttps://hdl.handle.net/20.500.12395/35731
dc.identifier.volume5en_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherInternational University of Sarajevoen_US
dc.relation.ispartofPeriodicals of Engineering and Natural Sciencesen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.selcuk20240510_oaigen_US
dc.subjectBipartite Table Methoden_US
dc.subjectDDFSen_US
dc.subjectDDSen_US
dc.subjectQuadratic Compressionen_US
dc.subjectVHDLen_US
dc.titleA high resolution DDFS design on VHDL using Bipartite table methoden_US
dc.typeArticleen_US

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