FPGA Based Fast Bartlett DoA Estimator for ULA Antenna Using Parallel Computing

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dc.contributor.authorUnlersen, Fahri M.
dc.contributor.authorYaldiz, Ercan
dc.contributor.authorImeci, Sehabeddin T.
dc.date.accessioned2020-03-26T19:54:01Z
dc.date.available2020-03-26T19:54:01Z
dc.date.issued2018
dc.departmentSelçuk Üniversitesien_US
dc.description.abstractThis paper presents a design and implementation of a structure which uses Bartlett Direction of Arrival (DoA) algorithm and a receiver system on Altera Cyclone IV and Cyclone III FPGAs. First of all, a software defined radio (SDR) that has 4 simultaneous inputs, is designed. All data used in this study are obtained by using this radio system. Then one of the FPGA is configured as antenna simulator and the other one is used for implementing Bartlett DoA estimation algorithm. Bartlett DoA estimation algorithm is developed completely in parallel and compared with a previous study which is performed sequentially on an FPGA using NIOS processor. The designs are tested by using 4-element Uniform Linear Array (ULA) antenna. Implemented hardware is compared in terms of DoA calculation speed and the sources that occupy on the FPGA. Furthermore, the paper has significant improvement in calculation duration thereby achieving lower response latency compared with previously published similar works.en_US
dc.identifier.endpage459en_US
dc.identifier.issn1054-4887en_US
dc.identifier.issn1943-5711en_US
dc.identifier.issue4en_US
dc.identifier.scopusqualityQ3en_US
dc.identifier.startpage450en_US
dc.identifier.urihttps://hdl.handle.net/20.500.12395/36644
dc.identifier.volume33en_US
dc.identifier.wosWOS:000432579800013en_US
dc.identifier.wosqualityQ4en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherAPPLIED COMPUTATIONAL ELECTROMAGNETICS SOCen_US
dc.relation.ispartofAPPLIED COMPUTATIONAL ELECTROMAGNETICS SOCIETY JOURNALen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.selcuk20240510_oaigen_US
dc.subjectBartlett algorithmen_US
dc.subjectdirection of arrival estimationen_US
dc.subjectFPGAen_US
dc.subjectparallel computingen_US
dc.titleFPGA Based Fast Bartlett DoA Estimator for ULA Antenna Using Parallel Computingen_US
dc.typeArticleen_US

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